Digital Logic
Q161.
Consider the following circuit involving three D-type flip-flops used in a certain type of counter configuration. If at some instance prior to the occurrence of the clock edge, P. Q and R have a value 0, 1 and 0 respectively, what shall be the value of PQR after the clock edge?Q163.
Consider the following state diagram and its realization by a JK flip flop The combinational circuit generates J and K in terms of x, y and Q.The Boolean expressions for J and K are :Q164.
In an SR latch made by cross-coupling two NAND gates, if both S and R inputs are set to 0, then it will result inQ166.
Consider the following circuit involving a positive edge triggered D FF. Consider the following timing diagram. Let Ai represent the logic level on the line A in the i-th clock period. Let A' represent the complement of A. The correct output sequence on Y over the clock periods 1 through 5 isQ167.
How many pulses are needed to change the contents of a 8-bit up counter from 10101100 to 00100111 (rightmost bit is the LSB)?Q168.
Consider the following circuit. The flip-flops are positive edge triggered D FFs. Each state is designated as a two-bit string Q0Q1 . Let the initial state be 00. the state transition sequence isQ169.
Consider the partial implementation of a 2-bit counter using T flip-flops following the sequence 0-2-3- 1-0, as shown below. To complete the circuit, the input X should beQ170.
The following arrangement of master-slave flip flops has the initial state of P, Q as 0, 1 (respectively). After three clock cycles the output state P, Q is (respectively),